1. Field of the Invention
The present invention relates to a circuit suitable for recovering (regenerating) clock and data from a received signal, in particular to a circuit arrangement for recovering clock and data from a received analog signal.
2. Related Art
In communication systems, there is frequently a requirement to recover the originally-transmitted data information and the corresponding clock information from a serial data stream of a received signal. This process is usually described as “Clock and Data Recovery” (CDR).
Data rates are continuously increasing. For example, communication between chips on a printed circuit board typically reach 3.125 Gb/s per channel, which consists of two differentially-driven and impedance-controlled traces. As a result of clock jitter, bandwidth limitations of the individual channels, intersymbol-interference (ISI) as well as reflections and crosstalk between the channels, the useful data “eye” opening is only 35% of the particular bit cell. In the above example of a 3.125 Gb/s data stream with NRZ (Non Return to Zero) modulated data, only a data “eye” opening with a length of 112 ps is available per bit cell, while the rest of the bit cell is disturbed by clock jitter, intersymbol interference, reflections, etc.
Irrespective of whether clock and data recovery relies on a delay locked loop (DLL) or phase locked loop (PLL), there are two basically different clock and data information from a received signal, namely sampling of the received signal with phase picking, and phase alignment.
In the case of phase alignment, the position of the sampling edge is adjusted to a 90° phase shift in relation to the received or input signal. The data is recovered by means of a pulsed decision element such as a synchronizing flip-flop.
In the case of sampling, the received signal is sampled several times at various timepoints via decision elements arranged in parallel. The output signal of one of the decision elements is subsequently selected as a regenerated data signal corresponding to the phase position of the received signal in relation to the reference signal, which explains the term “phase picking.”
A basic disadvantage of both such conventional methods is that, effectively, in each case only a small portion of the signal flows into the decision elements. This portion is determined based on the position of the clock edge of the sampled decision element and its setup and hold time. In order to minimize impairment to the setup and hold times of the sampled decision element, which can lead to its metastability and therefore to a logically undefined condition, the decision element is generally configured so that its setup and hold times are as short as possible. Therefore, the time segment actually evaluated around the clock edge is very small and, as a result, the signal output evaluated is very minute. High frequency interference, especially high frequency hum, on the supply voltage to the clock is and data recovery unit (CDR unit) or on the received signal leads to an increased bit error rate (BER), particularly when there is a small data “eye” opening.
Current integrating receivers are commonly used to reduce sensitivity to interference when small signal outputs are sampled. In such conventional apporaches, the differential data signal is integrated during the time duration of a bit cell. At the end of the bit cell an evaluation is made as to whether the integral is positive or negative to regenerate the data signal. The advantage of this approach is that the received signal is not sampled at a single timepoint, which could be disturbed by high frequency interference in such a way that the synchronizing flip-flop is metastable. Integration in this case acts as a low pass filter which suppresses any high frequency interference.
For communication systems with only a minimum useful data “eye” opening, for example in the region of 35% of the bit cell, a current integrating receiver of this type is, however, not suitable. This is because the distorted and disturbed signal portion (65% of the bit cell in the case of a data “eye” opening of 35%) that is outside the useful data “eye” opening would be overweighted.
Some conventional phase alignment CDR techniques readjust the phase of the sampling timepoint to the optimum point in the data “eye” center. Such CDR methods require phase detection, which evaluates the phase position of the received signal in relation to the momentary sampling time, and which provides the phase detection result as a control difference to a phase regulator. To execute such phase detection, the phase detector must evaluate the distorted and disturbed time-relevant segment of the received signal outside the useful data “eye” opening.
In the case of purely digital phase detectors, such as for example described in U.S. Pat. No. 4,218,771 and also called “Hogge type,” this disturbed time-relevant segment of the received signal is equally sampled by synchronizing flip-flops. As a result, the metastability rate of these flip-flops is correspondingly high. This metastability can then lead further to incorrect phase detection until it is hopefully cancelled by the next pulsing of the synchronizing flip-flops. Deficient phase detection of this kind leads to additional jitter of the sampling timepoint and, as a result, further constricts the useful data “eye” opening. The metastability problem also impairs more recent purely digital phase detectors, since basically metastability cannot be eliminated through synchronizers.
Conventional mixed analog/digital phase detectors obtain one of two input signals from a data synchronizing flip-flop. Due to the pulsing of the data synchronizing flip-flops, metastability occurs less often in the data “eye” center. However, such data synchronizing flip-flops can become metastable through high frequency interference at the moment of sampling. As a result, phase detection is equally disturbed in mixed analog/digital phase detectors as in the case of the purely digital phase detector.
To prevent individual metastability events from impairing clock and data recover, the single synchronizing flip-flop of such conventional phase detection systems have been replaced with a majority decision of several synchronizing flip-flops. Unfortunately, the time shift of the individual synchronization pulses inside the majority decision element principally has no clearly defined phase position, leading to phase uncertainty in the case of clock and data recovery. Therefore, a phase detector of the type described above, in which an input phase originates from the synchronized (that is to say regenerated) data signal is basically unsuitable for a majority decision by several synchronizing flip-flops.
For this reason, purely digital CDR methods working with sampling are normally used for implementing such a majority decision. In such devices, the data signal is fed to a number of digital synchronizing flip-flops. The flip-flops are pulsed with a multi-phase pulse so that each bit cell is acquired at several places. The synchronizing flip-flops subsequently search through the resulting digital data stream for signal changes by means of complex digital circuitry. To recover the phase information, the bits corresponding to the data “eye” center are selected based on the phase information (“phase picking”). The selected bits are subsequently combined into a parallel data stream.
In the case of a purely digital CDR method of this kind working with sampling, a massively-multiplied digital data stream therefore occurs. Ultimately, once the phase position has been recognized the greatest part of the digital data stream is rejected. Significant expenditures of energy for such kinds of digital CDR methods working with sampling for cost-favorable Gb/s communication systems, in which a number of channels ought to be integrated on one chip, and which nevertheless must function with only a minimum useful data “eye” width of typically 35%, is much too great.
This will be quantitatively described below by way of a simple example. For the simplest majority decision, such as “2 out of 3,” the sampling intervals of three synchronizer flip-flops active one after the other must divide the minimum data “eye” width by three. It is assumed that one of these could become active due to a phase error in sampling at the data “eye” edge and therefore metastable. If the minimum data “eye” width is 35% of the bit cell, the sampling interval must be 35%÷3=11.6% of the bit cell. Therefore, the bit cell must be divided by sampling into at least 8.57 parts. As a result, nine synchronizing flip-flops per bit cell are necessary. This increases the rate of the data stream by a factor 9, that is, a data stream with a bit rate of, for example, 3.125 Gb/s becomes a data stream of 28.125 Gb/s. This increased data rate has to be processed purely digitally. For adequate robustness of phase detection, a sufficiently large number of signal changes must be included in the evaluation. Thus, for example, to this end eight consecutive bit cells, that is to say, one byte, can be used. Therefore, an amount of 8×9=72 sampling points flow into the phase detection, and the space and energy requirement increases accordingly. Regarding its power capacity, although the purely digital CDF method working with sampling and phase selection is the best possible, since it is generally resistant to clock jitter, interference and metastability, this CDR method has the disadvantage of considerable space and energy requirement.
In summary, it can be stated that although with the purely digital CDR method working with sampling described and its variants a solution for the metastability problems is known from prior art, this purely digital solution brings with it disadvantageous space and energy requirements. The known mixed analog/digital methods on the other hand provide no solution to the metastability problems.
In the present invention, the inventor seeks to provide a clock and data recovery circuitry, whereby the advantageous sampling of the input or received signal will be maintained for recovering the data stream, without as a result increasing the data rate to be processed digitally so massively as is the case with the CDR circuit arrangements working with sampling known until now. Data regeneration as well as phase detection in this case ought to be as resistant as possible to metastabilities of synchronizing flip-flops, whereby especially the invention should be easy to implement from a circuitry aspect (for example using CMOS technology) and complex circuits, as for example adjustment of the pulse duty factor of the regenerated data signal to 50% known from the state of the art or equalization of delay times of the signal paths for data regeneration and phase detection etc. are eliminated.
In accordance with one aspect of the invention, a circuit arrangement to recover clock and data from a received signal is disclosed, comprising a commutator device for sampling the received signal in such a way that several sampling values of a bit cell, transmitted with the received signal, are distributed time-wise consecutively onto several output connections of the commutator device, and are emitted there in the form of corresponding intermediate signals, a first circuit for combining a first group of intermediate signals of the commutator device into a first uniting signal, which serves as the basis for data recovery, a second circuit for combining a second group of intermediate signals of the commutator device into a second uniting signal, which serves as the basis for clock recovery, and a phase regulator arrangement, to which is fed the second uniting signal and which, dependent on this, sets sampling phases for sampling the received signal assigned to the individual output connections of the commutator device.